8bit Multiplier Verilog Code Github -

On Xilinx FPGAs, the * operator automatically maps to a DSP48E block. For sequential multipliers, explicitly instantiate a DSP48E primitive for better performance.

// Instantiate a DSP macro for 8x8 signed multiply
DSP48E1 #(.A_INPUT("DIRECT"), .B_INPUT("DIRECT"))
   dsp_inst (.A(a_signed), .B(b_signed), .P(product));

module top_multiplier #(
    parameter ARCH_TYPE = "ARRAY"  // "ARRAY", "CARRY_SAVE", "WALLACE"
)(
    input  wire        clk,
    input  wire        rst_n,
    input  wire [7:0]  A,
    input  wire [7:0]  B,
    input  wire        start,
    output reg [15:0]  P,
    output reg         done
);
wire [15:0] product;
generate
    if (ARCH_TYPE == "ARRAY") begin
        multiplier_array u_mult (
            .A(A), .B(B), .P(product)
        );
    end else if (ARCH_TYPE == "CARRY_SAVE") begin
        multiplier_carry_save u_mult (
            .A(A), .B(B), .P(product)
        );
    end else begin
        multiplier_wallace u_mult (
            .A(A), .B(B), .P(product)
        );
    end
endgenerate
// Pipeline register for product output
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        P <= 16'b0;
        done <= 1'b0;
    end else if (start) begin
        P <= product;
        done <= 1'b1;
    end else begin
        done <= 1'b0;
    end
end

endmodule

module multiplier_array (
    input  wire [7:0] A,      // Multiplicand
    input  wire [7:0] B,      // Multiplier
    output wire [15:0] P      // Product
);
    wire [7:0] partial [0:7];
    wire [15:0] sum [0:7];
    wire [15:0] carry [0:7];
// Generate partial products
generate
    genvar i, j;
    for (i = 0; i < 8; i = i + 1) begin
        assign partial[i] = 8B[i] & A;
    end
endgenerate
// Adder tree implementation
// ... (full adder and half adder instantiations)

endmodule