If you find an older PDF of the 2nd edition, you miss the critical updates from Resve Saleh. The 3rd edition specifically addresses:
| Topic | Method | |-------|--------| | Inverter delay | ( t_p = 0.69 R_eq C_L ) (for step input) | | CMOS gate sizing | Match ( R_eq,p / R_eq,n ) to ( W_p / W_n ) | | Logical effort | ( g = R_gate/R_inv ) (same drive) | | Leakage estimation | ( I_sub = I_0 \cdot 10^(V_GS-V_TH)/S \cdot (1 - e^-V_DS/V_T) ) | | Dynamic power | ( P = \alpha C_L V_DD^2 f ) | | Clock skew margin | ( T_clk > t_pcq + t_logic + t_setup + t_skew ) |
Finding the PDF is easy (many university courses host it legally for enrolled students, though be wary of copyright on public sites). Using it is hard. Here is a study roadmap: If you find an older PDF of the
Week 1-2: Read Chapters 1-3. Simulate a single NMOS and PMOS in SPICE. Replicate the $I_D-V_DS$ curves.
Week 3-4: Master the Inverter (Ch 5). Calculate the propagation delay of an inverter driving a load of 50fF. Do not use a simulator first. Use the textbook formulas. | Topic | Method | |-------|--------| | Inverter
Week 5-6: Move to Logic Gates (Ch 7). Analyze the logical effort of a NAND gate versus a NOR gate. Understand why NAND is preferred in CMOS.
Week 7-8: Sequential Circuits and Timing (Ch 9). Draw the timing diagram for a master-slave flip-flop. Derive the minimum clock period. Finding the PDF is easy (many university courses
Final: Read Interconnect (Ch 13). Given a 10mm metal line, calculate the RC time constant. That calculation alone will explain why your CPU runs at 3GHz and not 300GHz.
