Kc89c72 Datasheet

The internal register architecture, as detailed in the KC89C72 datasheet, is identical to the AY-3-891x family. There are 16 readable/writable registers (R0–R15).

| Register | Function | |----------|-----------------------------------------------| | R0 | Tone A period (fine, bits 0–7) | | R1 | Tone A period (coarse, bits 8–11) | | R2 | Tone B period (fine) | | R3 | Tone B period (coarse) | | R4 | Tone C period (fine) | | R5 | Tone C period (coarse) | | R6 | Noise period (5-bit, bits 0–4) | | R7 | Mixer control (enable/disable tone/noise) | | R8 | Amplitude A (16 levels or envelope) | | R9 | Amplitude B | | R10 | Amplitude C | | R11 | Envelope period (fine) | | R12 | Envelope period (coarse) | | R13 | Envelope shape (attack/decay/cycle) | | R14 | I/O Port A data | | R15 | I/O Port B data |

Understanding this register map is critical for programming the KC89C72 — any complete datasheet includes these details with example code.

Since the original is missing, use these resources:

Example minimal C setup (SDCC-like pseudocode): kc89c72 datasheet

#include <kc89c72.h> // replace with actual device header
void main(void) 
    // Configure ports and peripherals
    TMOD = 0x20; // Timer1 in mode 2 (example)
    TH1 = 0xFD;  // Baud rate for UART (example)
    SCON = 0x50; // Configure UART
    TR1 = 1;     // Start Timer1
    while (1) 
        // main loop

The KC89C72 contains 16 addressable registers (0 to 15), though not all are fully used. Here is the standard register map:

| Register (A8 = 0-15) | Name | Function | | :--- | :--- | :--- | | 0 | Channel A Fine Tune | Lower 8 bits of tone period | | 1 | Channel A Coarse Tune | Upper 4 bits of tone period | | 2 | Channel B Fine Tune | Lower 8 bits | | 3 | Channel B Coarse Tune | Upper 4 bits | | 4 | Channel C Fine Tune | Lower 8 bits | | 5 | Channel C Coarse Tune | Upper 4 bits | | 6 | Noise Period | 5-bit noise frequency control | | 7 | Mixer / I/O Enable | Enable/disable tone/noise per channel, I/O control | | 8 | Channel A Volume | 4-bit volume (or envelope enable) | | 9 | Channel B Volume | Same as above | | 10 | Channel C Volume | Same as above | | 11 | Envelope Fine | Lower 8 bits of envelope period | | 12 | Envelope Coarse | Upper 8 bits (total 16-bit envelope period) | | 13 | Envelope Shape | Cycle, hold, alternate, attack patterns | | 14 | I/O Port A | Not used on KC89C72 (read returns 0xFF) | | 15 | I/O Port B | Not used |

Example: To set Channel A to middle C (~261 Hz) with a 1 MHz clock:

Q: Is the KC89C72 still in production?
A: No. It has been obsolete since the late 1990s. Only NOS (new old stock) or used pulls are available on eBay or surplus electronics sites. The internal register architecture, as detailed in the

Q: Can I replace a broken AY-3-8910 with a KC89C72?
A: Yes, in most cases. Both have identical pinouts and register sets. However, check the analog output impedance – the KC89C72 may require different external resistor values.

Q: The KC89C72 datasheet mentions “TEST1” and “TEST2” pins. How do I connect them?
A: Tie both directly to GND for normal operation. Leaving them floating may cause erratic behavior.

Q: Does the KC89C72 require external DACs?
A: No. The analog outputs (ANOD, BNOD, CNOD) are current outputs that directly drive a speaker or amplifier through a simple resistor and capacitor.

Q: Where can I find a full PDF of the KC89C72 datasheet?
A: Start with a Google search for “kc89c72 datasheet PDF”. The top results often include Alldatasheet and Datasheet4U. Be careful of subscription walls — many sites offer free previews. Since the original is missing, use these resources:

The KC89C72 (name pattern) is positioned as a general-purpose 8-bit microcontroller for consumer and industrial embedded applications: simple control, sensor interfacing, human–machine interfaces (buttons, LEDs, small displays), and basic communications. It targets low-cost, low-power systems where modest CPU performance and integrated I/O reduce bill-of-materials and firmware complexity.

The most critical section of any datasheet is the pinout diagram. For the KC89C72, the 28-pin configuration is straightforward.

Pinout Diagram (Top View, Notch Left)

| Pin | Name | Type | Description | | :--- | :--- | :--- | :--- | | 1 | DA7 | I | Data bus bit 7 (MSB) | | 2 | DA6 | I | Data bus bit 6 | | 3 | DA5 | I | Data bus bit 5 | | 4 | DA4 | I | Data bus bit 4 | | 5 | DA3 | I | Data bus bit 3 | | 6 | DA2 | I | Data bus bit 2 | | 7 | DA1 | I | Data bus bit 1 | | 8 | DA0 | I | Data bus bit 0 (LSB) | | 9 | /BDIR | I | Bus Direction (Control) | | 10 | /BC2 | I | Bus Control 2 | | 11 | /BC1 | I | Bus Control 1 | | 12 | Vss | Power | Ground (0V) | | 13 | CLOCK | I | Master Clock Input (Typically 1-2 MHz) | | 14 | /RESET | I | Low-Active Reset | | 15 | A8 | I | Address Line (used for register vs. data select) | | 16 | TEST1 | - | Factory test pin; tie to Vss normally | | 17 | TEST2 | - | Factory test pin; tie to Vss | | 18 | ANO | O | Analog noise output (rarely used – tie to Vss) | | 19 | ENO | O | Envelope generator output (digital monitor) | | 20 | CHB | O | Channel B square wave (before D/A) | | 21 | CHC | O | Channel C square wave | | 22 | CHA | O | Channel A square wave | | 23 | NC | - | No connection | | 24 | Vdd | Power | +5V | | 25 | /IOA | O | I/O Port A (not implemented, tie high via resistor) | | 26 | /IOB | O | I/O Port B (not implemented, tie high) | | 27 | DAC | O | Analog output (use external resistor network) | | 28 | REF | I | Reference voltage for D/A (usually Vdd/2 via divider) |

Important Note for Designers: On the KC89C72, pins 25 and 26 (/IOA, /IOB) are not functional as general-purpose I/O (unlike the AY-3-8910). Pull them to Vdd through 10k resistors.